Beat 01
The loss
Inspection at cell test generated far more calls than the quality team could disposition, so real excursions waited behind nuisance while panels kept being made.
Case Studies
These are illustrative deployment shapes built from discovery interviews and design-partner scoping. Numbers are targets, clearly labelled, not audited results.
Deployment shapes across line types
Shape 01
Beat 01
Inspection at cell test generated far more calls than the quality team could disposition, so real excursions waited behind nuisance while panels kept being made.
Beat 02
One inspection line. mura-and-defect in shadow mode for eight weeks, trained on the fab's own true-versus-false-call history.
Beat 03
Classification separates large-area non-uniformity, sub-pixel opens and shorts, particles and stains, and attaches the evidence behind every retained call.
Beat 04
False-call rate and escape rate together — suppression that costs escapes is not a win. Both are measured against the pre-shadow baseline. [TARGET]
# closed loop, one panel
perceive substrate → tft → emitter stack → sub-pixel
plan deposition · anneal · transfer · test/bin
act recipe write-back (SECS-GEM)
sense mura ΔL* · sub-pixel opens · particles
optimise yield · ramp · scrap
log immutable audit entry ✓ signed
retrain engineer correction → model
Shape 02
Beat 01
Thickness and overlay drift accumulated across mother glass for hours before showing as visible non-uniformity, producing predictable rework every ramp.
Beat 02
One deposition tool set. deposit-and-pattern in advisory mode with twin validation before any recommended recipe change.
Beat 03
Chamber telemetry and metrology fused into a drift trajectory; corrections simulated in the twin, approved by process integration, written back over SECS-GEM.
Beat 04
Percentage of panels produced inside the uniformity window, and rework rate, against the baseline quarter. [TARGET]
# closed loop, one panel
perceive substrate → tft → emitter stack → sub-pixel
plan deposition · anneal · transfer · test/bin
act recipe write-back (SECS-GEM)
sense mura ΔL* · sub-pixel opens · particles
optimise yield · ramp · scrap
log immutable audit entry ✓ signed
retrain engineer correction → model
Shape 03
Beat 01
Mass-transfer losses at millions of emitters per panel turned every fractional yield point into repair cycles or scrapped backplanes.
Beat 02
One transfer and repair cell. microled-transfer in advisory, with repair prioritisation by recovered value.
Beat 03
Placement and bonding parameters learned against measured outcomes; repair queue ordered by value rather than arrival.
Beat 04
Transfer yield and repair cycles per panel, plus cost per good panel. [TARGET]
# closed loop, one panel
perceive substrate → tft → emitter stack → sub-pixel
plan deposition · anneal · transfer · test/bin
act recipe write-back (SECS-GEM)
sense mura ΔL* · sub-pixel opens · particles
optimise yield · ramp · scrap
log immutable audit entry ✓ signed
retrain engineer correction → model
Method
The method matters more than the number. This is the one we would sign up to.
Step 1 of 6 · define
One metric, already reported, with an owner.
Step 2 of 6 · baseline
A full production period before any write-back.
Step 3 of 6 · shadow
Predictions logged and scored against your dispositions.
Step 4 of 6 · assist
Engineers approve; overrides captured with reasoning.
Step 5 of 6 · compare
Same products, same shifts, same criteria.
Step 6 of 6 · publish
Nothing leaves your fab without written approval.
At a glance
All figures are design-partner targets, not audited outcomes.
| Shape | Line type | Agent | Primary metric |
|---|---|---|---|
| Mura false-call reduction | Gen-6 flexible OLED | mura-and-defect | False-call rate / escape rate |
| Deposition drift control | Rigid OLED | deposit-and-pattern | In-window rate / rework |
| Transfer yield | microLED pilot | microled-transfer | Transfer yield / repair cycles |
| Ramp acceleration | Automotive display | yield-and-ramp | Weeks to target yield |
What we will not do
It is easy to publish a 40% improvement with no baseline, no method and no name. We will not. Every number on this page is labelled as a target until a design partner consents to publishing a measured result.
# closed loop, one panel
perceive substrate → tft → emitter stack → sub-pixel
plan deposition · anneal · transfer · test/bin
act recipe write-back (SECS-GEM)
sense mura ΔL* · sub-pixel opens · particles
optimise yield · ramp · scrap
log immutable audit entry ✓ signed
retrain engineer correction → model
Voices from the line
“We do not lose panels because nobody is watching. We lose them because the signal that mattered was buried under a thousand nuisance calls.”
“Ramp is the whole game. If a new product takes two quarters of manual tuning, that is two quarters of margin we never get back.”
“Transfer yield is our ceiling on microLED. Every dead emitter is a repair cycle or a scrapped backplane.”
Quotes are illustrative composites drawn from discovery interviews with process-integration, yield and quality engineers. Named references are [PLACEHOLDER] pending design-partner consent.
The economics
Emiteon is priced and evaluated on the numbers a fab already reports. These are design-partner targets for the first twelve months of deployment.
Figures marked as targets are design-partner objectives, not audited results. Company operating status, customers and outcomes are [ASPIRATIONAL] until independently verified.
FAQ
Through three gates. Shadow mode observes and predicts with no write-back; advisory mode recommends recipe, transfer and binning moves that a process-integration or yield engineer approves; graduated autonomy releases low-risk deposition, anneal and transfer control once measured accuracy and twin validation clear the bar. High-impact decisions stay human-in-the-loop.
Reducing false calls is the wedge, not a side effect. The mura-and-defect agent is trained on true-versus-false-call labels from your own inspection history, so it separates genuine large-area non-uniformity, sub-pixel opens and shorts, particles and stains from nuisance signals, and every call is traceable to the evidence behind it.
Per-tenant isolation with recipes, panel designs and defect images scoped to your tenant, encryption in transit and at rest, SSO/RBAC, an immutable yield/quality-grade audit log and an on-prem or air-gapped option. Fleet learning shares model improvements, never your recipes.
Deposition, photolithography, encapsulation and anneal tools, Mura/AOI inspection and metrology, array and cell test, mass-transfer and repair stations, robotic handling and MES — vendor-neutral via SECS-GEM/HSMS where the tool supports it, with REST and OPC-UA bridges elsewhere.
Every pixel, perfectly uniform.
Bring the workflow. We will bring the method and the honesty about what it shows.